1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a nonvolatile ferroelectric memory and a method for fabricating the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described. FIG. 3a is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. As the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
With reference to FIG. 3b, the reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory. If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. In other words, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transited on an xe2x80x9cfxe2x80x9d state as shown by hysteresis loop of FIG. 1. If the data is not destroyed, xe2x80x9caxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value xe2x80x9c1xe2x80x9d is output in case that the data is destroyed while the logic value xe2x80x9c0xe2x80x9d is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
A related art nonvolatile ferroelectric memory and a method for fabricating the nonvolatile ferroelectric memory will now be described. FIG. 4a is a diagram that illustrates a layout of a related art nonvolatile ferroelectric memory.
Referring to FIG. 4a, the related art nonvolatile ferroelectric memory is provided with a first active region 41 and a second active region 41a asymmetrically formed at fixed intervals. A first wordline W/L1 is formed to cross the first active region 41, and a second wordline W/L2 is formed to cross the second active region 41a spaced a distance from the first wordline W/L1. A first bitline B/L1 is formed in a direction to cross the first and second wordlines at one side of the first active region 41, and a second bitline B/L2 is formed parallel to the first bitline B/L1 to cross the first and second wordlines at one side of the second active region 41a. A first ferroelectric capacitor FC1 is formed over the first wordline W/L1 and the second wordline W/L2 and is connected to the first active region 41. A second ferroelectric capacitor FC2 is formed over the first wordline W/L1 and is electrically connected to the second active region 41a. A first plate P/L1 is formed over the first wordline W/L1 and is electrically connected to the first ferroelectric capacitor FC1, and a second plate line P/L2 is formed over the second wordline W/L2 and is electrically connected to the second ferroelectric capacitor FC2. FIG. 4a is a diagram that illustrates a layout of a unit cell, wherein the related art nonvolatile ferroelectric memory has the first and second ferroelectric capacitors FC1 and FC2 formed extending along a bitline direction, and the first plateline P/L1 formed over the first wordline W/L1 and the second plateline P/L2 formed over the second wordline W/L2.
FIG. 4b is a diagram that illustrates a cross-section across line I-Ixe2x80x2 in FIG. 4a. Referring to FIG. 4b, the related art nonvolatile ferroelectric memory is provided with a substrate 51 having an active region and a field region defined thereon, a first wordline 54 and a second wordline 54a formed over the active region and the field region with a first insulating layer 53 disposed inbetween, the first source/drain impurity regions 55 and 56 formed on both sides of the first wordline 54. Second source/drain impurity regions (not shown) are formed on both sides of the second wordline 54a. A second insulating layer 57 is formed on an entire surface inclusive of the first and second wordlines 54 and 54a having a contact hole exposing the first drain impurity region 56, and a first plug layer 58a is stuffed in the contact hole. A first metal layer 59 connects the first plug layer 58a and the first bitline (not shown). A third insulating layer 60 is formed on an entire surface inclusive of the first metal layer 59 having a contact hole exposing the first source impurity region 55, and a second plug layer 62 is stuffed in the contact hole. A barrier metal layer 63 is electrically connected to the second plug layer 62 and extended horizontally over the first wordline to the second wordline 54a. A lower electrode 64 of the first ferroelectric capacitor FC1 is formed on the barrier metal layer 63, a ferroelectric film 65 and an upper electrode 66 of the first ferroelectric capacitor are stacked on the lower electrode 64 of the first ferroelectric capacitor FC1 in succession. A fourth insulating layer 67 is formed on an entire surface inclusive of the upper electrode 66 of the second ferroelectric capacitor. A first plate line 68 is formed over the first wordline 54 and electrically connected to the upper electrode 66 of the first ferroelectric capacitor FC1 through the fourth insulating layer, and a second plate line 68a formed over the second wordline 54a spaced from the first plate line 68.
A method for fabricating the related art nonvolatile ferroelectric memory of FIGS. 4a-4b will now be described. FIGS. 5axcx9c5f are diagrams that illustrate cross-sections showing the steps of a method for fabricating the related art nonvolatile ferroelectric memory shown alone line I-Ixe2x80x2 in FIG. 4a. As shown in FIG. 5a, a portion of a semiconductor substrate 51 is etched to form a trench, and an insulating film is stuffed in the trench to form a device isolation device 52. A first insulating layer 53 is formed on the substrate in the active region inclusive of the device isolation layer 52. A wordline material layer is formed on the first insulating layer 53, and patterned to form first and second wordlines 54 and 54a at fixed intervals.
As shown in FIG. 5b, the wordlines 54 and 54a are used as masks in implanting impurity ions to form a source impurity region 55 and a drain impurity region 56 having a conduction type opposite to the substrate 51. The source/drain impurity regions 55 and 56 are source/drain impurity regions of the first transistor T1 that takes the first wordline 54 as a gate electrode. Then, a second insulating layer 57 is formed on an entire surface of the substrate 51 inclusive of the first and second wordlines 54 and 54a. A photoresist layer (not shown) is coated on the second insulating layer 55 and patterned, and the patterned photoresist layer is used as a mask in selectively etching the second insulating layer 57 to form a contact hole 58 exposing the drain impurity region 56.
As shown in FIG. 5c, a conductive material is stuffed in the contact hole to form a first plug layer 58a, and first metal layer 59 is formed to connect the first plug layer 58a and the first bitline B/L1. Though not shown, the second bitline B/L2 is electrically connected to the drain impurity region of the second transistor T2.
As shown in FIG. 5d, a third insulating layer 60 is formed on an entire surface inclusive of the fist metal layer 59. A photoresist layer (not shown) is coated on the third insulating layer 60, patterned and used as mask in selectively etching the third insulating layer to form a contact hole 61 exposing the source impurity region 55.
As shown in FIG. 5e, a conductive material is stuffed in the contact hole 61 to form a second plug layer 62 electrically connected to the source impurity region 55. A barrier metal layer 63 is formed to be electrically connected to the second plug layer 62 and a lower electrode 64 of the first ferroelectric capacitor FC1. The lower electrode 64, a ferroelectric film 65 and upper electrode 66 of the first ferroelectric capacitor are successively formed on the barrier metal layer 63.
As shown in FIG. 5f, a fourth insulating layer 67 is formed on the upper electrode 66 of the first ferroelectric capacitor and selectively etched by photolithography to form a contact hole exposing a portion of the upper electrode 66 of the first ferroelectric capacitor FC1. Upon formation of a first plate line 68 connected with the upper electrode 66 of the first ferroelectric capacitor through the contact hole, the related art process for fabricating nonvolatile ferroelectric memory is completed. A second pulse line 68a is also shown in FIG. 5f. 
As described above, the related art nonvolatile ferroelectric memory and the related art method for fabricating the same have various disadvantages. A requirement to form the lower electrode of a capacitor thicker for increasing a sectional area of the lower electrode for securing capacitance causes a problem in that etching of the lower electrode is difficult because the lower electrode of the capacitor is formed of metal. Accordingly, there is a limitation in securing the capacitance coming from the limit of forming a thicker lower electrode of the capacitor. Further, the fabrication process is very difficult because the plate line should be formed in a small space so that a sufficient space is secured distinguishing the plate line from a wordline in an adjacent cell as the wordline and the plate line are formed in every unit cell. In addition, an increase of RC delay of the wordlines is not favorable in embodying a fast nonvolatile ferroelectric memory by decreasing an operational speed.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that reduces a RC delay of a wordline.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that increases an operational speed.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that reduces a device size.
Another object of the present invention is to provide a nonvolatile ferroelectric memory and a method for fabricating the same that reduces a RC delay of a split wordline for providing a fast device with an increased operational speed and a reduced device size.
To achieve at least these objects and other advantages in whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a nonvolatile ferroelectric memory having a unit cell with first and second bitlines, first and second transistors, and first and second ferroelectric capacitors, includes a first split wordline that crosses the first and second bitlines and is coupled to a gate of the first transistor and a first electrode of the second ferroelectric capacitor, a second split wordline that crosses the first and second bitlines and is coupled to a gate of the second transistor and a first electrode of the first ferroelectric capacitor, first shunt lines of a plurality of separated layers over the first split wordline and coupled to the first split wordline, and second shunt lines of a plurality of separated layers over the second split wordline and coupled to the second split wordline.
To further achieve the above objects in a whole or in part, there is provided a method for fabricating a nonvolatile ferroelectric memory that includes (1) forming first and second split wordlines on a semiconductor substrate, (2) forming plural layers of first and second shunt lines over the first and second split wordlines, respectively, (3) forming a first electrode of the second ferroelectric capacitor over the first shunt lines, and forming a first electrode of the first ferroelectric capacitor over the second shunt lines, (4) forming a ferroelectric layer and the second electrode of the first ferroelectric capacitor on the first electrode of the first ferroelectric capacitor in succession, and forming a ferroelectric layer and the second electrode of the second ferroelectric capacitor on the first electrode of the second ferroelectric capacitor in succession, (5) electrically coupling the second electrode of the first ferroelectric capacitor and the active region at one side of the first split wordline, and electrically coupling the second electrode of the second ferroelectric capacitor and the active region at one side of the second split wordline, and (6) electrically coupling the first shunt lines and the first electrode of the second ferroelectric capacitor to the first split wordline, and electrically coupling the second shunt lines and the first electrode of the first ferroelectric capacitor to the second split wordline.
To further achieve the above objects in a whole or in part, there is provided a ferroelectric memory having a plurality of unit cells, wherein each unit cell includes first and second bitlines extending in a first direction, first and second transistors, first and second ferroelectric capacitors, a first split wordline extending in a second direction to cross the first and second bitlines, wherein the first split wordline is coupled to a control electrode of the first transistor and a first electrode of the second ferroelectric capacitor, a second split wordline extending in the second direction to cross the first and second bitlines and coupled to a control electrode of the second transistor and a first electrode of the first ferroelectric capacitor, at least one first shunt line extending in the second direction and coupled to the first split wordline and at least one second shunt line extending in the second direction and coupled to the second split wordline.
To further achieve the above objects in a whole or in part, there is provided a ferroelectric memory that includes a first active region and a second active region defined in a semiconductor substrate, first and second split wordlines that respectively cross the active regions, first shunt lines in first and second insulating layers over the first split wordline, second shunt lines in the first and second insulating layers over the second split wordline, a first electrode of a second ferroelectric capacitor over the first shunt lines, wherein the first electrode of the second ferroelectric capacitor is coupled to the first split wordline and the first shunt lines and a first electrode of a first ferroelectric capacitor over the second shunt lines, wherein the first electrode of the first ferroelectric capacitor is coupled to the second split wordline and the second shunt lines.
To further achieve the above objects in a whole or in part, there is provided a method for fabricating a ferroelectric memory that includes forming first and second split wordlines on a semiconductor substrate, forming at least one layer of first and second shunt lines over the first and second split wordlines, respectively, forming a second ferroelectric capacitor over the at least one first shunt line and a first ferroelectric capacitor over the at least one second shunt line, electrically coupling a second electrode of the first ferroelectric capacitor and a first active region in the substrate at one side of the first split wordline, and electrically coupling a second electrode of the second ferroelectric capacitor and a second active region in the substrate at one side of the second split wordline and electrically coupling the at least one first shunt line and a first electrode of the second ferroelectric capacitor to the first split wordline, and electrically coupling the at least one second shunt line and a first electrode of the first ferroelectric capacitor to the second split wordline.
To further achieve the above objects in a whole or in part, there is provided a method for fabricating a ferroelectric memory that includes defining a first active region and a second active region on a semiconductor substrate, forming first and second split wordlines extending along a first direction to cross the first and second active regions, respectively, defining sources and drains in the active regions on both sides of the first and second split wordlines, respectively, forming first plugs respectively coupled to the drains respectively and forming second plugs respectively coupled to the sources, forming plural layers including first shunt lines over the first split wordlines and second shunt lines over the second split wordline, forming first and second ferroelectric capacitors over the first and second shunt lines, respectively, each being a second electrode over a ferroelectric layer over a first electrode, electrically coupling the second electrodes of the first and second ferroelectric capacitors to corresponding ones of the second plugs and coupling the first shunt lines and the first electrode of the second ferroelectric capacitor to the first split wordline, and coupling the second shunt lines and the first electrode of the first ferroelectric capacitor to the second split wordline.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.